The invention relates in general to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same, wherein leakage current occurring due to a parasitic bipolar transistor by a triple well structure at the time of erasure can be prevented.
An NAND flash memory device performs data program by injecting electrons into the floating gate by Fowler-Nordheim (FN) tunneling. The NAND flash memory device provides a large capacity and a high level of integration.
The NAND flash memory device includes a number of cell blocks. Each cell block includes a number of cell strings in which a number of cells for storing data are connected in series to form one string, and a drain select transistor and a source select transistor formed between the cell string and the drain, and the cell string and the source, respectively. Each cell block further includes a peri region in which a number of circuit elements for generating a predetermined bias for the program, erasure, and read operations of a cell and transferring the bias are formed.
Furthermore, cells that constitute different cell strings and are driven by the same word line (WL) form a page. Gates of a number of drain select transistors are commonly connected to a drain select line (DSL) and are driven by the potential of the drain select line. Gates of a number of source select transistors are commonly connected to a source select line and are driven by the potential of the source select line.
The NAND flash memory cell includes a gate in which a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate are laminated in a predetermined region of a semiconductor substrate, and a junction formed on the semiconductor substrate at both sides of the gate.
A NAND flash memory device constructed as described above is an electrically programmable and erasable device, and it performs program and erase functions in such a manner that electrons vary the threshold voltage while being moved due to a strong electric field through a thin tunnel oxide layer.
The NAND flash memory device implements erasure on a block basis. For the purpose of erasure, it is necessary that a ground voltage (Vss) be applied to the entire word lines of a selected cell block and a high voltage of about 20 V be applied to the well.
As described above, the NAND flash memory device performs the erasure operation by applying a high voltage typically of about 20 V, to the well. Accordingly, the semiconductor substrate of the cell region must have a triple well structure. That is, an N well is formed on a P-type semiconductor substrate and a P well is formed on an N well, thereby forming the triple well structure. In this case, a parasitic bipolar transistor is formed between the semiconductor substrate, the N well, and the P well.
The parasitic bipolar transistor keeps turned off with a high voltage not being applied to the well. However, if a high voltage of about 20 V is applied to the well for erasure, the parasitic bipolar transistor is turned on and the leakage current is generated accordingly. More particularly, a great amount of leakage current is generated at the boundary of the cell region and the peri region. The leakage current causes to drop an erase voltage, resulting in the failure of the erase operation.